A novel method that converts a semiconductor Transient Thermal Impedance Curve (TTIC) into an equivalent thermal R-C network model is presented. Thermal Resistance (R) and thermal Capacitance (C) parameters of the model are identified using manufacturer's data and off line Recursive Least Mean Square techniques. Relevant estimation theory concepts and the formulation of an appropiate model for the identification process are given. Model synthesis is illustrated using an isolated base power transistor module. The application of time decoupled theory for high order thermal models is outlined. Simulation of junction temperature responses using model and manufacturer TTIC's are compared. Estimated parameter validity is further confirmed by parameter calculation obtained from module physical dimensions.
This application of identification techniques to the estimation of thermal overloading in integrated circuit design first appeared in the IEEE Trans. on Power Electronics in April 1991.
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